What is VHDL| Introduction & History of VHDL| VHDL tutorial for Beginers |TechWithCode

Before knowing What is VHDL, You should know what is HDL first.

what is HDL

HDL stands for Hardware Description Language.it describes the functions of hardware like how the hardware will perform after certain input.

Full-Form of VHDL

VHDL stands for VHSIC Hardware Description Language
                                  where VHSIC stands for (Very High-Speed Integrated Circuit)

What is VHDL

VHDL stands for VHSIC Hardware Description Language
here VHSIC stands for (Very High-Speed Integrated Circuit)

This language is used to design electronics hardware and test that hardware on the computer like what will the output if you give an input. It makes the hardware implementation easy and reduces the cost of implementation because when you design hardware manually then it may have a possibility to perform wrong after implementation and once your machine performs wrong all your hard work and equipment get worst.
so to avoid this difficulty VHDL(VHSIC Hardware Description Language) come forward. In the VHDL(VHSIC Hardware Description Language) engineer write logical code in the computer according to the requirement then VHDL Simulator(VIVADO) will automatically give you the RTL diagram of your machine.in that Simulator, you can also check how my hardware will perform in the computer. if you were satisfied with the output then you can build the hardware as per the RTL diagram.

Sample code of  VHDL

Some example code of VHDL(VHSIC Hardware Description Language) is given below so you can have some idea about code in VHDL.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and1_df is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end and1_df; architecture dataflow of and1_df is begin C<=A AND B; end dataflow;
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History OF VHDL

VHDL(VHSIC Hardware Description Language) was originally developed in 1983. American Department of Defense initiated the development of VHDL because they face problem in order to document the behavior of the ASIC

(An application-specific integrated circuit is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed to run in a digital voice recorder )

that supplier companies were including in equipment. the US military needed a standardized method of describing electronic systems.
before VHDL(VHSIC Hardware Description Language) US military many face difficulty identify the internal functions of the component of weapon which is supplied by the other company because they don't know the process of designing , what type of coding and functionality they have added in the weapon.
                                               To know the internal functions of a component of weapon, the US military was initiated the development of one standard hardware description language called VHDL. all companies have to follow this standard language to develop the hardware.

What does VHDL do?

VHDL is standard languages which is used to specifying verifying designing of electronics.

and helps to create model of digital system (an entity),Simple logic gate, ALU, comparator or as complex as a complete electronic system

VHDL Modelling Style:-

There are three type of modelling style in VHDL which used to write an architecture.

1. Dataflow
2. Behavioral
3. Structural

DataFlow Modelling style:

•  In Dataflow modelling style ,we only uses the set of concurrent assignment statements

• Dataflow modelling style describe the system by showing how the data flow through the system.
• we directly use gate-level-implementaion in Dataflow modelling style
• It have one or more concurrent signal assignment statements.
• Example code of Half adder in Dataflow modelling style is given bellow:

library ieee; use ieee.std_logic_1164.all; entity half_adder is port (a, b: in std_logic; sum, carry_out: out std_logic); end half_adder; architecture dataflow of half_adder is begin sum <= a xor b; carry_out <= a and b; end dataflow;

Behavioral Modelling style:

• Behavioral modelling style describes the behavior of system step by step.
• Behavioral modelling style uses one or more process statement in VHDL code.
• Each process statements contains one or more concurrent signal assignment statements
• Example code of Half adder in Behavioral modelling style is given bellow:

library ieee; use ieee.std_logic_1164.all; entity half_adder is port (a, b: in std_logic; sum, carry_out: out std_logic); end half_adder; architecture behavior of half_adder is begin ha: process (a, b) begin if a = ‘1’ then sum <= not b; carry_out <= b; else sum <= b; carry_out <= ‘0’; end if; end process ha; end behavior;

Structural Modelling style:

• The entity of Structural Modelling style described as set of interconnected components.
• This modeling style is used in complex designing projects
• In the Structural Modelling style, Top level design's architecture describes the interconnection of lower level design
• Basically this model is used into complex system design in which many small entity are going to used, this modelling style allow to design and verify each entity independetly before using in the main complex project.
• Example code of Half adder in Structural modelling style is given bellow:

library ieee; use ieee.std_logic_1164.all; entity half_adder is -- Entity declaration for half adder port (a, b: in std_logic; sum, carry_out: out std_logic); end half_adder; architecture structure of half_adder is -- Architecture body for half adder component xor_gate -- xor component declaration port (i1, i2: in std_logic; o1: out std_logic); end component; component and_gate -- and component declaration port (i1, i2: in std_logic; o1: out std_logic); end component; begin u1: xor_gate port map (i1 => a, i2 => b, o1 => sum); u2: and_gate port map (i1 => a, i2 => b, o1 => carry_out); -- We can also use Positional Association -- => u1: xor_gate port map (a, b, sum); -- => u2: and_gate port map (a, b, carry_out); end structure;

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