vhdl code for full adder using Behavioral Model | VHDL tutorial | TechWithCode.com

What is full adder.

Full Adder is a Logical circuit which adds three inputs and produces two outputs of binary numbers. The first two inputs are A0 and A1 and the third input is a carry bit as A2. The outputs are C as a carry bit and S as sum bit.

Implementing Full Adder using Behavioral Modelling:-

VHDL code for RTL Diagram of Full adder:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FULL_ADDER_BEV is Port ( A : in STD_LOGIC_VECTOR (2 downto 0); S : out STD_LOGIC; C : out STD_LOGIC); end FULL_ADDER_BEV; architecture Behavioral of FULL_ADDER_BEV is begin process (A) begin 53 if(A="000") then S <= '0'; C <= '0'; elsif(A="001" or A="010" or A="100") then S <= '1'; C <= '0'; elsif(A="111") then S <= '1'; C <= '1'; else S <= '0'; C <= '1'; end if; end process; end Behavioral;

RTL diagram for Full adder:- 

After running the above code in VHDL Simulator, then you got this desing

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VHDL code for Simulation of Full adder:-

entity FULL_ADDER_BEV_TB is end FULL_ADDER_BEV_TB; architecture Behavioral of FULL_ADDER_BEV_TB is component FULL_ADDER_BEV is Port ( A : in STD_LOGIC_VECTOR (2 downto 0); S : out STD_LOGIC; C : out STD_LOGIC); end component; signal A : STD_LOGIC_VECTOR (2 downto 0) := "000"; signal S : STD_LOGIC; signal C : STD_LOGIC; begin uut: FULL_ADDER_BEV port map ( A => A, S => S, C => C ); stim_proc: process begin wait for 100ns; A <= "001"; wait for 100ns; A <= "010"; wait for 100ns; A <= "011"; wait for 100ns; A <= "100"; wait for 100ns; A <= "101"; wait for 100ns; A <= "110"; wait for 100ns; A <= "111"; wait; end process; end Behavioral;

Waveform of Full adder:-

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