VHDL code for half adder using Dataflow | RTL Diagram , Simulation Code, Test Bench, Waveform | VHDL Complete Tutorial by TechWithCode

In This article, we will show you the VHDL Code of half adder using the Dataflow model.it contains VHDL code for RTL Diagram, Simulation Code and the waveform Half adder. During the execution of code, I have used Xilinx VIVADO  Software.

To understand the code, you should have the knowledge of the following Things.

1. Introduction & History of VHDL
2. VHDL Modelling Style
3. What is Dataflow Modelling Style in VHDL
4. What is Behavioral Modelling Style in VHDL
5. What is Structural Modelling Style in VHDL
6. Operators in VHDL
7. How to write a VHDL Program in Dataflow Modelling Style

What is Half Adder?

Half adder is a logical circuit that adds two binary digits and produces two outputs as sum and carry; XOR is applied to both inputs to produce the sum bit (S) and AND gate is applied to both inputs to produce carry bit (C) as shown in the picture below.

Half Adder

Logical Expression of Half Adder:-

out = not (A) 

Implementing Half Adder using Dataflow Modelling:-

• we directly use gate-level-implementation in Dataflow modeling style
• To know more about DataFlow model, click here

VHDL code for RTL Diagram of Half Adder:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity half_adder_df is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end half_adder_df; architecture Behavioral of half_adder_df is begin s <= a xor b; c <= a and b; end Behavioral;

RTL Diagram of Half Adder:-

After executing the above code you will get following RTL Digram.

VHDL code for Simulation of Half Adder:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity half_adder_df_tb is end half_adder_df_tb; architecture dataflow of half_adder_df_tb is component half_adder_df is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end component; signal a :std_logic :='0'; signal b :std_logic :='0'; signal s :std_logic ; signal c :std_logic ; begin uut:half_adder_df port map (a=>a,b=>b,s=>s,c=>c); stim_proc: process begin wait for 150ns; b <= '1'; wait for 150ns; a <= '1'; b <= '0'; wait for 150ns; b <= '1'; wait; end process; end dataflow;

Author @ Deepak Yadav

WaveForm of Half Adder:-

After executing the above code you will get the following WaveForm.

To know how to write code in VHDL using the DataFlow modeling style, please watch the following video.

        

Related:

1.  Full adder in VHDL using Behavioral Model | RTL, Simulation, TestBentch and Waveform 

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