VHDL Code of NOT Gate using Dataflow model | RTL Diagram , Simulation Code, Test Bench, Waveform | VHDL Complete Tutorial by TechWithCode

In This article, we will show you the VHDL Code of NOT gate using the Dataflow model.it contains VHDL code for RTL Diagram, Simulation Code and the waveform. During the execution of code, I have used Xilinx VIVADO  Software.

To understand the code you should have the knowledge of the following Things.

1. Introduction & History of VHDL
2. VHDL Modelling Style
3. What is Dataflow Modelling Style in VHDL
4. What is Behavioral Modelling Style in VHDL
5. What is Structural Modelling Style in VHDL
6. Operators in VHDL
7. How to write a VHDL Program in Dataflow Modelling Style

What is NOT gate

This is a logical circuit that inverts the input and sent it to the output.

Circuit Diagram of NOT gate.

Logical Expression of NOT gate:-

out = not (A) 

Implementing NOT gate using Dataflow Modelling:-

• we directly use gate-level-implementation in Dataflow modeling style
• To know more about DataFlow model, click here

VHDL code for RTL Diagram of NOT gate:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NOT1_DF is Port ( A : in STD_LOGIC; B : out STD_LOGIC); end NOT1_DF; architecture Dataflow of NOT1_DF is begin B <= not A; end Dataflow;

RTL Diagram of NOT gate:-

After executing the above code you will get following RTL Digram.

VHDL code for Simulation of NOT gate:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NOT1_DF_TB is end NOT1_DF_TB; architecture DATAFLOW of NOT1_DF_TB is component NOT1_DF is Port ( A : in STD_LOGIC; B : out STD_LOGIC); end component; signal A :std_logic :='0'; signal B :std_logic; begin uut: NOT1_DF port map (A=>A,B=>B); stim_proc: process begin wait for 150ns; A<='1'; wait; end process; end DATAFLOW;

WaveForm of NOT gate:-

After executing the above code you will get the following WaveForm.

To know how to write code in VHDL using the DataFlow modeling style, please watch the following video.

        

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