VHDL Code of OR Gate using Dataflow model | RTL Diagram , Simulation Code, Test Bench, Waveform | VHDL Complete Tutorial by TechWithCode

VHDL Code of OR Gate using Dataflow model:-  In this article, We will provide you  VHDL Code of OR gate using Dataflow modeling With Full Explanation.

To Understand the VHDL code of OR gate, We need to know some basic things which are explained below.

What is OR gate

when any input is SET the output is SET otherwise RESET.


Boolean Expression of OR gate

out = A + B

Implementing OR gate using Dataflow Modelling:-

  • we directly use gate-level-implementation in Dataflow modelling style
  • To know more about DataFlow model, click here
Or gate 

VHDL code for RTL Diagram of OR gate :-

RTL Diagram of OR Gate:-

After executing the above code you will get following RTL Digram.

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VHDL code for Simulation of OR Gate:-

Waveform of FullAdder:-

After executing the above code you will get the following WaveForm.

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To know how to write code in VHDL using DataFlow modelling style, please watch the following video.

          
Also Read:

2How to write a VHDL program in Behavioral Modelling Style

3AND Gate code in VHDL using Dataflow Model |  RTL, Simulation ,TestBentch and Waveform 

4Full adder in VHDL using Behavioral Model | RTL, Simulation ,TestBentch and Waveform 

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