VHDL Code of Ripple Carry Adder using Structural model | RTL Diagram , Simulation Code, Test Bench, Waveform | VHDL Complete Tutorial by TechWithCode

Before writing VHDL code for Ripple Carry Adder, WE should have knowledge about what Ripple Carry Adder is? and how it works.It will help us to understand the VHDL Code Of Ripple Carry Adder.

What is Ripple Carry Adder?

Ripple Carry Adder is a combinational logic circuit which is used for two n-bit binary numbers.
It requires n full adders in its circuit for adding two n-bit binary numbers.
that means if you want to add 4 bit two binary number then you need to have 4 Full adder.

Circuit Diagram Ripple Carry Adder:-

How Ripple Carry Adder works:-

Ripple Carry Adder works in different stages.
Each full adder takes the carry-in as input and produces carry-out and sum bit as output. This carry-out serves as carry-in to its adjacent full adder As shown in the above picture.

Approach to Write VHDL Code of Ripple Carry Adder using Structural model:-

First of all, if you do not know about Structural model then I strongly recommend to please read This Post First: What is Structural model how to code in the structural model in VHDL

So.

      As we know , In Ripple Carry Adder , We need full adder so During code writing we also use the full adder code so make sure you made a Full adder before making Ripple Carry adder. 

Related :- VHDL code for full adder

VHDL code for RTL Diagram of Ripple Carry Adder:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RCA_STRUCT is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; cout : out STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0)); end RCA_STRUCT; architecture structural of RCA_STRUCT is component full_adder_df is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end component; signal t : std_logic_vector ( 2 downto 0); begin i1: full_adder_df port map(a(0),b(0),cin,s(0),t(0)); i2: full_adder_df port map(a(1),b(1),t(0),s(1),t(1)); i3: full_adder_df port map(a(2),b(2),t(1),s(2),t(2)); i4: full_adder_df port map(a(3),b(3),t(2),s(3),cout); end structural;

RTL Diagram of Ripple Carry Adder:-

After executing the above code you will get following RTL Digram.

VHDL code for Simulation of Ripple Carry Adder:-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RCA_STRUCT_TB is end RCA_STRUCT_TB; architecture Behavioral of RCA_STRUCT_TB is component RCA_STRUCT is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; cout : out STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0)); end component; signal a: std_logic_vector(3 downto 0):="0000"; signal b: std_logic_vector(3 downto 0):="0001"; signal cin: std_logic :='0'; signal cout: std_logic ; signal s: std_logic_vector(3 downto 0); begin utt:RCA_STRUCT port map (a=>a,b=>b,cin=>cin,cout=>cout,s=>s); stim_proc:process begin wait for 200ns; a<="0001"; b<="0010"; cin<='1'; wait for 200ns; a<="0010"; b<="0011"; cin<='0'; wait for 200ns; a<="1000"; b<="1001"; cin<='1'; wait; end process; end Behavioral;

WaveForm of Ripple Carry Adder:-

After executing the above code you will get the following WaveForm.

To know how to write code in VHDL, please watch it

          

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