VHDL programming tutorial beginners to advance | How to write any program in VHDL for RTL Diagram, simulation,test bench, waveform

To write a program in any language you have to have the knowledge about the syntax, about the operators and the way how to arrange them.
So today I will try to make you a perfect coder so you can write any program in the VHDL.

Before writing a program for any logic circuit, you must have some knowledge about that circuit like what that circuit will do, how it is designed, what component has used to build that circuit and the most important is the truth table which will decide that what is output this circuit is producing.

If you want to see step by step practical with full explanation, I strongly suggest you that please watch the following video.

Step 1:- Open our VHDL editor

One of the best software to develop logic circuits is VIVADO.It is quit fast as compare to others.

when you open this it's interface is very user-friendly..

Step 1:- Click on Create Project

Give the name of your project.

Step 2:- Select RTL project and Click on NEXT

Step 3:- Create Source file and Click on NEXT

Give file name as your project but i recommend you to keep tha file name Same as the projecta name

Step 4:-Select Board and Click on NEXT and Finish

Select Category, Family, Package, Speed, Temperature and Static power as shown in the figure below

and select the bottom-most part.
Now VIVADO will create a project for you with some prewritten code
Till now all above process is same for any type of project.

Your prewritten code should look like this:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand1_bev is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           c : out STD_LOGIC);
end nand1_bev;

architecture Behavioral of nand1_bev is

begin


end Behavioral;

Step 5:- create port according to the circuit then finish

For example . i am making NAND gate using the behavioral model in VHDL programming so
we have to declare the ports for the NAND gate.
for nand gate, as we know we need total 3 port
2 input port
and
1 output port

Now the workplace is created

Step 6:- Write the code according to the circuit requirement.

here we have to write code after begin
first of all, we create a process that will take all the input port as an input.
every process in VHDL will have two keywords begin and end process;
all the code will be written between these two keywords

example:-

we are creating NAND gate. In the NAND gate, we know that if all inputs are 1 then output is 0. otherwise output is 1.

So now your VHDL code should be like this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand1_bev is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           c : out STD_LOGIC);
end nand1_bev;

architecture Behavioral of nand1_bev is

begin
process(a,b)
begin
if(a='1' and b='1')then
c<='0';
else
c<='1';
end if;
end process;

end Behavioral;

Step 7:- Now save the project and run it to show RTL design.

This is our design of the hardware NAND gate after running the above code.

VHDL programming tutorial beginners to advance | How to write any program in VHDL for RTL Diagram, simulation,test bench, waveform

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now we have to write the simulation code to test this hardware..

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8. Created simulation file or Test-bench

9. Go to add source or click on + symbol

10. Choose simulation file

11. Give a name to the simulation file.

In my case name is nand_gate_beh_tb, here tb stands for Testbench

12. Do not give any port address

Here we do not give any port address, because we have to test it. we will give the input at run time and check whether it is working well or not.

13.Copy entity portion which has port declaration from our RTL code and into the testbench file

14.Replaced the entity with component

After step 12 you will have some pre-written code. from that code, you have to Replaced the entity with component

15. create signals for all the ports which will communicate with our design

create signals for all the ports which will communicate with our design

16. Port mapping

now we have to do the port mapping with signals after begin keyword you have to write
Port map basicaly istablish the connection to designed port map.

17. Create a process which will change the value of input ports

we have to create a process which will change the value of a & b port

18. After doing all steps your simulation code

After doing all steps your simulation code should look like this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand1_bev_tb is
   
end nand1_bev_tb;

architecture Behavioral of nand1_bev_tb is
 component nand1_bev is
  Port ( a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : out STD_LOGIC);
end component;
signal a:std_logic:='0';
signal b:std_logic:='0';
signal c:std_logic;

begin
uut:nand1_bev port map
(a=>a,b=>b,c=>c);
stim_proc:process
begin
wait for 100ns;
b<='1';
wait for 100ns;
b<='0';
a<='1';
wait for 100ns;
b<='1';
wait;
end process;


end Behavioral;

19. Explanation of above code:-

uut stands for unit under test
during the signal creation we have initialized the signal by 0 0
so it will take time to process this data that's why we have to wait for some time after every input
c is the output port thats why we can not initialize it
now chage the value of a and b.
previously it was a=0, b=0;
now we have to change a=0, b=1;-

20.Now save it and run the simulation.

After running the simulation file you got the waveform.

In the case of NAND gate, it looks like this

Thanks you..